1. Field of the Invention
The present invention relates to the reliability of connection holes between wirings formed within a semiconductor device, and more particularly to a semiconductor device having a much higher reliability than a conventional connection hole structure and a method of fabricating the same.
2. Description of the Prior Art
Recently, as the degree of integration of semiconductor devices has advanced, wiring layers have tended to be produced with finer dimensions and their number has multiplied.
At the present, leading the progress of finer dimension technology of semiconductor devices, semiconductor memories have been developed by making use of multilayer wiring technology.
Multilayer wiring technology employs a polycide film with two layers of polycrystalline silicon and a refractory metal silicide. It is, however, difficult to obtain multilayer wiring with aluminum alloy film when multiple layers and finer dimension layers are desired. Therefore, a single layer is used for forming a wiring layer with aluminum alloy film.
However, the sheet resistance of a wiring layer using polycide film is about one hundred fold higher than the sheet resistance of a wiring layer of aluminum alloy film. Accordingly, when manufacturing a semiconductor device which operates at high speed, a wiring delay due to polycide film occurs. Thus, in comparison with a semiconductor device comprised of aluminum alloy film, a semiconductor device comprised of polycide film, capable of operating at high speed, is not obtained. It is hence important to realize both fine dimension and multiple layers using aluminum alloy film with a low sheet resistance, thereby maintaining the reliability of the semiconductor device using it.
In addition, along with the progress of finer dimension technology, there is a trend which relates to finer dimension technology in the field of microcomputer devices such as logic, Application Specific Integrated Circuit (ASIC), and gate arrays. In particular, in the field relating to microprocessing units (hereinafter called the MPU), the operating speed and function of the MPU are upgraded progressively. Therefore, the development of finer dimension technology for microcomputer devices is expected to be developed. CPU performance varies with the size of the data to be handled. For example, in the same 32-bit MPUs, the performance is determined by the constraints imposed as a result of the provided function and its operating frequency, that is, the maximum processing speed.
At present, the operating frequency for a 32-bit MPU is about 50 MHz. The degree of integration of a 32-bit MPU is realized by forming 1,000,000 transistors in an area of 15 mm .times. 15 mm or less. Moreover, in order to raise the operating frequency and in order to realize high functionality with an MPU, an enhancement in the degree of integration is indispensable. Accordingly, a more sophisticated finer technology is needed.
In the field of MPUs, in order to operate at high speed as well as to realize high function, attempts have been made to avoid the lowering of operating speed due to wiring delay. For this purpose, hitherto, multilayer wiring using aluminum alloy film has been employed. To improve the performance of the MPU, therefore, it is important to increase the dimensional fineness achievable with multilayer wiring technology using aluminum alloy film.
Several problems which result from increased dimensional fineness of wiring using aluminum alloy film are deterioration and breakdown of wiring by migration. Such reliability problems relating to semiconductor devices are major factors which impede the progress of improved dimensional fineness technology.
Migration is classified into two areas: electromigration and stress migration. Much has been reported relating to the deterioration phenomenon which results in wiring as a result of stress migration. For example, stress migration is described in the 25th Annual Proceedings Reliability Physics 1987, pp. 15-21, "The Effect of Cu Addition to Al--Si interconnects on Stress Induced Open-Circuit Failure." Stress migration occurs when wiring, comprised of aluminum alloy film, is subjected to the stress of an interlayer dielectric film surrounding the wiring and the passivation film and the temperature history in the particular circumstances. As a result of the stress and temperature history, the aluminum atoms in the aluminum alloy film are moved. In the resulting positions of the moved aluminum atoms, cavities (called voids) are formed in the wiring. As the voids grow, the wiring is finally broken down. This phenomenon is called stress migration. In the above article, the addition of copper elements to aluminum alloy film is described. As a result, copper elements precipitate into the interface of the crystal grains of the aluminum film, thereby suppressing movement of aluminum atoms. It has thus been reported that the resistance to stress migration has been improved. This reported case is realized by paying attention to the wiring of the aluminum alloy film.
On the other hand, for finer dimension multilayer wiring technology using aluminum alloy film, as the width of wiring is reduced, it is simultaneously necessary to reduce the size of connection holes for connecting upper and lower wirings. The diameter of the connection holes for connecting upper and lower wirings must be smaller than the minimum width of the upper and lower wirings. For example, if the width of the wiring is 1.0 .mu.m, the diameter of the connection hole must be 1.0 .mu.m or less. If connection holes are used which have a diameter which is greater than the minimum width of the wiring, the width of the wiring is limited by the size of the connection holes. Accordingly, the density of the wiring cannot be raised easily, and the degree of integration cannot be enhanced. Hence, the chip size is larger if semiconductor devices having the same functions are used.
The prior art is described below with reference to the drawings. FIG. 8 is a process sectional view showing a prior art method of manufacturing a semiconductor device in the prior art. A first conductive type semiconductor substrate is exemplified by P-type semiconductor substrate 1. In the P-type semiconductor substrate 1, it is assumed in the following explanation that the semiconductor elements of an ordinary MOS transistor, a MOS capacitor, a bipolar transistor and resistance is formed (not shown).
On the P-type semiconductor substrate 1, a silicon oxide film forms a first interlayer dielectric film layer 2. The silicon oxide film is for example, SiO.sub.2 film, BPSG (Boron-Phospho-Silicate Glass) film, or PSG (Phospho-Silicate Glass) film formed using low pressure chemical vapor deposition or atmospheric pressure chemical vapor deposition techniques.
Next, a specified position of the first interlayer dielectric film layer 2 is selectively removed. A first connection hole 4 is formed in the removed region. The P-type semiconductor substrate 1 is exposed on the bottom of the first connection hole 4. The native oxide film formed on the exposed semiconductor substrate 1 is removed. Afterwards, a first conductive film layer 3 is formed in the specified region including the first connection hole 4 (FIG. 8A). This first conductive film layer 3 is formed in a desired pattern by anisotropic etching such as Reactive Ion Etching (hereinafter called RIE). Later, heat treatment is effected at a temperature of about 450.degree. C. (FIG. 8B).
In succession, a second interlayer dielectric film layer 6 is formed on the first conductive film layer 3.
Next, a specified position of a second interlayer insulation film layer 6 is removed selectively. The removed region becomes a second connection hole 5. A native oxide film is formed on the first conductive film layer 3 exposed on the bottom of the second connection hole 5. By removing this native oxide film, the surface of the first conductive film layer 3 is exposed. A second conductive film layer 7 is formed in a specified region at least including the second connection hole 5 (FIG. 8C). The second conductive film layer 7 is formed of an aluminum alloy film.
The second conductive film layer 7 is formed in a desired pattern by an anisotropic etching method such as RIE (FIG. 8D).
By this fabricating method, a two-layer wiring structure is realized.
Afterwards, a passivation film on the semiconductor element is formed with a film thickness of 500 to 1200 nm.
In a semiconductor device fabricated by the conventional method, degradation phenomenon due to high temperature storage at 180.degree. C. occurs as explained below. A semiconductor device is fabricated for measuring the degree of deterioration. The conditions with which the semiconductor device is fabricated is explained below. As a first interlayer dielectric film layer 2, a BPSG film is deposited on the P-type semiconductor substrate in a film thickness of 60 nm. A first conductive film layer 3 is deposited on the BPSG film. A second interlayer dielectric film layer 6 is formed thereon. A second connection hole 5 is formed in the second interlayer dielectric film layer 6. As a second conductive film layer 7, an aluminum alloy film is deposited with a film thickness of 1000 nm. As a passivation film, a PSG film having a thickness of 300 nm and a silicon nitride film having a thickness of 800 nm are formed.
FIG. 9 shows the relation between the contact hole size and the open failure rate of a second connection hole.
As the high temperature storage time is increased to 180.degree. C., the open failure rate increases. After standing for 1600 hours, if the diameter of second connection hole 5 is smaller than about 1.4 .mu.m, the open failure rate increases suddenly. That is, in the prior art, although the conductive state is established immediately after manufacture, failure in the semiconductor device occurs by standing at a temperature of 180.degree. C. When the diameter of the connection hole is smaller than a specific size, open failure results, which poses a serious problem for reliability.
Thus, in the composition of the prior art, in a semiconductor device with multilayer wiring, when the diameter of the second connection hole 5 becomes small, serious reliability problems result.
When multilayer wiring comprised of a fine dimensional structure is manufactured in a semiconductor device of the prior art, in addition to wiring breakage due to stress migration, open failure of connection holes occurs, and a serious reliability problem takes place for connection holes having a diameter of about 1.4 .mu.m or less.
Failed semiconductor devices have been analyzed by use of a focused ion beam (FIB) technique. As a result it was found that voids were formed in the aluminum alloy film which is the second conductive film layer 7, at the interface between the first conductive film layer 3 in the second connection hole 5 and the aluminum alloy film as the second conductive film layer 7. When voids are thus formed, the aluminum alloy film which is the second conductive film layer 7 is eliminated. In this way, it was determined that disconnection was the cause of the open failure.
The same problem occurs when copper elements are preliminarily added to the aluminum alloy film.
The correlation between open failure rate and passivation film stress have also been investigated in order to search the cause of open failure. The stress of the passivation film was varied by the type of the passivation film. As a result of measurement of the semiconductor device having a passivation film comprised of two layers of PSG film of 300 rim in thickness and silicon nitride film of 800 nm in thickness, a semiconductor device having the passivation film comprised of a single layer of PSG film of 300 rim in thickness, a semiconductor device having a passivation film composed of a single layer of silicon nitride of 800 nm in thickness, and a semiconductor device without a passivation film, the PSG film formed by atmospheric pressure chemical vapor deposition method had a tensile stress of 2.times.10.sup.-9 dynes/cm.sup.2, and the silicon nitride film formed by plasma enhanced chemical vapor deposition method had a compressive stress of 9.times.10.sup.-9 dynes/cm.sup.2.
FIG. 10 shows the cumulative open failure of each semiconductor device after high temperature storage at 180.degree. C. in nitrogen atmosphere and after standing for 1000 hours.
In a semiconductor device without passivation film, the cumulative open failure was not increased, while a semiconductor device which is formed with a silicon nitride film with a strong compressive stress demonstrated an obvious increase in cumulative open failure.
In the prior art, the second conductive film layer 7 was formed by sputtering. Accordingly, in the second connection hole 5, the coverage of the second conductive film layer 7 is poor. Hence, the thickness of the second conductive film layer 7 in the second connection hole 5 is very thin. Accordingly, due to the stress of the passivation film in the upper part, the aluminum atoms are moved, and voids are formed in the second connection hole 5, thereby easily leading to open failure.
As a method of improving the coverage of the second conductive film layer 7, the technique of burying the second connection hole 5 in a conductive film layer is known. For example, by burying tungsten, the coverage of the second conductive film layer 7 in the second connection hole 5 may be notably improved. In the case of tungsten burying, however, the resistance value of tungsten is increased by about ten-fold as compared with the case using the conventional aluminum alloy film. Due to such resistance increase, wiring delays occur, which may lead to operating error of the semiconductor device. It is hence necessary to plan the design again by taking the resistance increase into consideration. Yet, the conventional design asset cannot be used directly.
The above problem, that is, occurrence of voids in the second connection hole 5, may be easily avoided by forming the second conductive film layer 7 of a refractory metal such as tungsten. Since the melting point is high in tungsten and other refractory metal, the wire is not easily broken by the stress of the passivation film. However, tungsten and other refractory metals are higher in resistivity as compared with aluminum alloy film, and have increased wiring resistance.
It is hence an object of the invention to present a constitution in which the second conductive film layer is not moved easily by the stress of the upper passivation film. It is another object of the invention to prevent the occurrence of voids in the second connection hole. It is a further object of the invention to suppress the increase of wiring resistance to a minimum. It is a further object of the invention to present a semiconductor device particularly free from reliability problems if the diameter of the connection hole in the multilayer wiring using aluminum alloy film is smaller than about 1.4 .mu.m. A manufacturing method is also disclosed.